# title
Arm Cortex-M3 Processor Technical Reference Manual Revision r2p1

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ARM Cortex-M3 Processor Technical Reference Manual

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List of differences in functionality between r0p0 and r1p0

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List of differences in functionality between r1p0 and r1p1

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List of differences in functionality between r1p1 and r2p0

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List of differences in functionality between r2p0 and r2p1

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Binary compatibility with other Cortex processors

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Base register update in LDM and STM operations

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Interrupt Controller Type Register, ICTR

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Debugger actions for identifying the processor

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Data and instruction address compare resources

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TraceEnable Control 1 Register, ETMTECR1 characteristics

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Device Power-Down Status Register, ETMPDSR

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Integration Test Miscellaneous Inputs, ITMISCIN

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ETM Integration Test ATB Control 2, ETM_ITATBCTR2

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ETM Integration Test ATB Control 0, ETM_ITATBCTR0

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Asynchronous Clock Prescaler Register, TPIU_ACPR

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Formatter and Flush Status Register, TPIU_FFSR

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Formatter and Flush Control Register, TPIU_FFCR

# metadata.contentDescription
This book contains documentation for the Cortex-M3 processor, describing the programmers model, instructions, registers, memory map, cache and debug support. Components include ETM, MPU, NVIC, FPB, DWT, ITM, AHB, and TPIU.