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ARM Cortex-A72 MPCore Processor Technical Reference Manual r0p3

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ARM Cortex-A72 MPCore Processor Technical Reference Manual

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Advanced Microcontroller Bus Architecture (AMBA)

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About the Cortex-A72 processor functions

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ARM  Cortex-A72 MPCore Processor
Integration Manual

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AArch64 virtual memory control registers

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AArch32 Processor Feature Register 0, EL1

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AArch32 Processor Feature Register 1, EL1

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AArch32 Auxiliary Feature Register 0, EL1

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AArch32 Memory Model Feature Register 0, EL1

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AArch32 Memory Model Feature Register 1, EL1

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AArch32 Memory Model Feature Register 2, EL1

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AArch32 Memory Model Feature Register 3, EL1

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AArch32 Instruction Set Attribute Register 0, EL1

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AArch32 Instruction Set Attribute Register 1, EL1

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AArch32 Instruction Set Attribute Register 2, EL1

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AArch32 Instruction Set Attribute Register 3, EL1

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AArch32 Instruction Set Attribute Register 4, EL1

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AArch32 Instruction Set Attribute Register 5, EL1

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AArch64 Processor Feature Register 0, EL1

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AArch64 Instruction Set Attribute Register 0, EL1

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AArch64 Memory Model Feature Register 0, EL1

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Virtualization Processor ID Register, EL2

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Virtualization Multiprocessor ID Register, EL2

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Architectural Feature Access Control Register, EL1

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Architectural Feature Trap Register, EL2

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Architectural Feature Trap Register, EL3

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Virtualization Translation Control Register, EL2

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Auxiliary Fault Status Register 0, EL1 and EL3

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Auxiliary Fault Status Register 1, EL1 and EL3

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Exception Syndrome Register, EL1 and EL3

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Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register

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Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register

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Auxiliary Memory Attribute Indirection Register, EL1 and EL3

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Auxiliary Memory Attribute Indirection Register, EL2

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Configuration Base Address Register, EL1

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Architectural Feature Access Control Register

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Translation Table Base Register 0 and Register 1

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Instruction cache speculative memory accesses

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Strictly-enforced inclusion property with L1 data caches

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Register slice support for large cache sizes

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Generic Interrupt Controller CPU Interface

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CPU interface System register descriptions

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Virtual interface control register summary

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Virtual interface control register descriptions

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Virtual CPU interface register descriptions

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External Debug Auxiliary Control Register

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External Debug Integration Output Control Register

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External Debug Integration Input Status Register

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External Debug Integration Mode Control Register

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ROM table Debug Peripheral Identification Registers

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ROM table Debug Component Identification Registers

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Performance Monitors Control Register, EL0

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Performance Monitors Common Event Identification Register 0, EL0

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Performance Monitors Control Register, EL0

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Performance Monitors Program Counter Sample Register

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Performance Monitors Context ID Sample Register

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Performance Monitors Virtual Context Sample Register

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Performance Monitors Snapshot Status Register

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Performance Monitors Overflow Status Snapshot Register

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Performance Monitors Cycle Counter Snapshot Register

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Performance Monitors Event Counters Snapshot Registers

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Performance Monitors Snapshot Control Register

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Performance Monitors Snapshot Reset Register

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CTI Integration Test Channel In Acknowledge register

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CTI Integration Test Trigger In Acknowledge register

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CTI Integration Test Channel Out register

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CTI Integration Test Trigger Out register

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CTI Integration Test Channel Out Acknowledge register

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CTI Integration Test Trigger Out Acknowledge register

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CTI Integration Test Channel In register

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CTI Integration Test Trigger In register

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ETM trace generation options and resources

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Address Comparator Access Type Registers

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Context ID Comparator Control Register 0

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Trace Integration Miscellaneous Outputs Register

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Trace Integration Miscellaneous Input Register

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Trace Integration Test ATB Data Register 0

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Trace Integration Test ATB Control Register 2

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Trace Integration Test ATB Control Register 1

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Trace Integration Test ATB Control Register 0

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Interaction with debug and the Performance Monitor Unit

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Interaction with the Performance Monitor Unit

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Effect of debug double lock on trace register access

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Programmers model for Advanced SIMD and Floating-point

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Floating-point Exception Control Register 32, EL2

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Floating-point Status and Control Register

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Transmit request virtual channel signals

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Transmit response virtual channel signals

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Receive response virtual channel signals

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Load or store accesses that span a page boundary

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A32 BKPT instruction with condition code not AL

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Address match breakpoint match only on second halfword of an instruction

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Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100

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Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111

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Address mismatch breakpoint match only on second halfword of an instruction

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Address mismatch breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111

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Other mismatch breakpoint matches any address in current mode and state

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Link to nonexistent breakpoint or breakpoint that is not context-aware

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Address-matching Vector catch on 32-bit T32 instruction at vector-2

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Address-matching  Vector catch on 32-bit T32 instruction at vector+2

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Address-matching Vector catch and Breakpoint on same instruction

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DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a doubleword

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A32 HLT instruction with condition code not AL

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Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed

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Unlinked Context matching and Address mismatch breakpoints taken to Abort mode

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Vector catch on Data or Prefetch Abort, and taken to Abort mode

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H > N or H = 0 at Non-secure EL1 and EL0, including value read from PMCR_EL0.N

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H > N or H = 0: value read back in MDCR_EL2.HPMN

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P ≥ M and P ≠ 31: reads and writes of PMXEVTYPER_EL0 and PMXEVCNTR_EL0

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P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL

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P = 31: reads and writes of PMXEVCNTR_EL0

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n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0

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Exiting Debug state while instruction issued through EDITR is in flight

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Using memory-access mode with a non-word-aligned address

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Access to memory-mapped registers mapped to Normal memory

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Not word-sized accesses or (AArch64 only) doubleword-sized accesses

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External debug write to register that is being reset

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Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE

# metadata.contentDescription
This document describes the ARM Cortex-A72 processor.