# title
Instruction Set Assembly Guide for Armv7 and earlier Arm architectures Reference Guide

# topic.label
Instruction Set Assembly Guide for Armv7 and earlier Arm architectures Reference Guide

# topic.topics[].topics[].topics[].label
Changing between A32 and T32 instruction set states

# topic.topics[].topics[].topics[].label
Processor modes, and privileged and unprivileged software execution

# topic.topics[].topics[].topics[].label
Processor modes in Armv6-M, Armv7-M, and Armv8-M

# topic.topics[].topics[].topics[].label
General-purpose registers in AArch32 state

# topic.topics[].topics[].topics[].label
Predeclared core register names in AArch32 state

# topic.topics[].topics[].topics[].label
Predeclared extension register names in AArch32 state

# topic.topics[].topics[].topics[].label
Current Program Status Register in AArch32 state

# topic.topics[].topics[].topics[].label
Saved Program Status Registers in AArch32 state

# topic.topics[].topics[].topics[].label
Access to the inline barrel shifter in AArch32 state

# topic.topics[].label
Advanced SIMD and Floating-point Programming

# topic.topics[].topics[].topics[].label
Extension register bank mapping for Advanced SIMD in AArch32 state

# topic.topics[].topics[].topics[].label
Views of the Advanced SIMD register bank in AArch32 state

# topic.topics[].topics[].topics[].label
Conditional execution of A32/T32 Advanced SIMD instructions

# topic.topics[].topics[].topics[].label
Floating-point exceptions for Advanced SIMD in A32/T32 instructions

# topic.topics[].topics[].topics[].label
Advanced SIMD data types in A32/T32 instructions

# topic.topics[].topics[].topics[].label
Normal, long, wide, and narrow Advanced SIMD instructions

# topic.topics[].topics[].topics[].label
Extended notation extension for Advanced SIMD

# topic.topics[].topics[].topics[].label
Advanced SIMD system registers in AArch32 state

# topic.topics[].topics[].topics[].label
When to use flush-to-zero mode in Advanced SIMD

# topic.topics[].topics[].topics[].label
The effects of using flush-to-zero mode in Advanced SIMD

# topic.topics[].topics[].topics[].label
Advanced SIMD operations not affected by flush-to-zero mode

# topic.topics[].topics[].topics[].label
Extension register bank mapping for floating-point in AArch32 state

# topic.topics[].topics[].topics[].label
Views of the floating-point extension register bank in AArch32 state

# topic.topics[].topics[].topics[].label
Conditional execution of A32/T32 floating-point instructions

# topic.topics[].topics[].topics[].label
Floating-point exceptions for floating-point in A32/T32 instructions

# topic.topics[].topics[].topics[].label
Floating-point data types in A32/T32 instructions

# topic.topics[].topics[].topics[].label
Extended notation extension for floating-point code

# topic.topics[].topics[].topics[].label
Floating-point system registers in AArch32 state

# topic.topics[].topics[].topics[].label
When to use flush-to-zero mode in floating-point

# topic.topics[].topics[].topics[].label
The effects of using flush-to-zero mode in floating-point

# topic.topics[].topics[].topics[].label
Floating-point operations not affected by flush-to-zero mode

# topic.topics[].topics[].topics[].label
Updates to the condition flags in A32/T32 code

# topic.topics[].topics[].topics[].label
Floating-point instructions that update the condition flags

# topic.topics[].topics[].topics[].label
Condition code suffixes and related flags

# topic.topics[].topics[].topics[].label
Comparison of condition code meanings in integer and floating-point code

# topic.topics[].topics[].topics[].label
Benefits of using conditional execution in A32 and T32 code

# topic.topics[].topics[].topics[].label
Example showing the benefits of conditional instructions in A32 and T32 code

# topic.topics[].topics[].topics[].label
Syntax of Operand2 as a register with optional shift

# topic.topics[].topics[].topics[].label
MRS (system coprocessor register to general-purpose register)

# topic.topics[].topics[].topics[].label
MSR (general-purpose register to system coprocessor register)

# topic.topics[].topics[].topics[].label
Summary of shared Advanced SIMD and floating-point instructions

# topic.topics[].topics[].topics[].label
Interleaving provided by load and store element and structure instructions

# topic.topics[].topics[].topics[].label
Alignment restrictions in load and store element and structure instructions

# topic.topics[].topics[].topics[].label
VCVT (between fixed-point or integer, and floating-point)

# topic.topics[].topics[].topics[].label
VCVT (from floating-point to integer with directed rounding modes)

# topic.topics[].topics[].topics[].label
VCVTB, VCVTT (between half-precision and double-precision)

# topic.topics[].topics[].topics[].label
VLDn (single n-element structure to one lane)

# topic.topics[].topics[].topics[].label
VLDn (single n-element structure to all lanes)

# topic.topics[].topics[].topics[].label
VMOV (between two general-purpose registers and a 64-bit extension register)

# topic.topics[].topics[].topics[].label
VMOV (between a general-purpose register and an Advanced SIMD scalar)

# topic.topics[].topics[].topics[].label
VQDMLAL and VQDMLSL (by vector or by scalar)

# topic.topics[].topics[].topics[].label
VSTn (single n-element structure to one lane)

# topic.topics[].topics[].topics[].label
VCVT (between floating-point and integer)

# topic.topics[].topics[].topics[].label
VCVT (from floating-point to integer with directed rounding modes)

# topic.topics[].topics[].topics[].label
VCVT (between floating-point and fixed-point)

# topic.topics[].topics[].topics[].label
VCVTB, VCVTT (between half-precision and double-precision)

# topic.topics[].topics[].topics[].label
VFMA, VFMS, VFNMA, VFNMS (floating-point)

# topic.topics[].topics[].topics[].label
VMOV (between one general-purpose register and single precision floating-point register)

# topic.topics[].topics[].topics[].label
VMOV (between two general-purpose registers and one or two extension registers)

# topic.topics[].topics[].topics[].label
VMOV (between a general-purpose register and half a double precision floating-point register)

# metadata.contentDescription
This document contains an overview of the Arm architecture and information on A32 and T32 instruction sets. For assembler-specific features, such as additional pseudo-instructions, see the documentation for your assembler.