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ARM CoreLink CCN-502 Cache Coherent Network Technical Reference Manual r0p1

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ARM CoreLink CCN-502 Cache Coherent Network Technical Reference Manual

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About the CCN-502 Cache Coherent Network

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PCIe master and slave restrictions and requirements

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Error detection, signaling, and reporting

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Parity error reporting, poisoning, and logging

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Node configuration register address mapping

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Requirements of configuration register reads and writes

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Debug event module register descriptions

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Programming requirements for designs with an alternative path to the HN-I memory space

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QoS class and POCQ resource availability

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Software configurable memory region locking

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Error reporting and software configured error injection

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Single-bit ECC error tracking and interrupt

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Bottleneck analysis at SBSX and HN-I bridges

# metadata.contentDescription
This book is for the ARM CoreLink CCN-502 Cache Coherent Network. The CCN-502 is a scalable coherent interconnect based on the AMBA 5 CHI architecture. It is designed for use in high-end networking and enterprise compute systems.