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Arm Cortex-A73 MPCore Processor Technical Reference Manual r1p0

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Arm Cortex-A73 MPCore Processor Technical Reference Manual

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About the Cortex-A73 processor functions

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Advanced SIMD and Floating-point support

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Advanced SIMD and Floating-point support

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AArch64 virtual memory control registers

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AArch32 Instruction Set Attribute Register 0

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AArch32 Instruction Set Attribute Register 1

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AArch32 Instruction Set Attribute Register 2

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AArch32 Instruction Set Attribute Register 3

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AArch32 Instruction Set Attribute Register 4

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AArch32 Instruction Set Attribute Register 5

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AArch64 Instruction Set Attribute Register 0, EL1

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AArch64 Instruction Set Attribute Register 1, EL1

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AArch64 Memory Model Feature Register 0, EL1

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Architectural Feature Access Control Register

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Architectural Feature Trap Register, EL2

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Architectural Feature Trap Register, EL3

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Monitor Debug Configuration Register, EL3

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Virtualization Translation Control Register, EL2

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Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3

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Auxiliary Fault Status Register 0, EL1, EL2 and EL3

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Auxiliary Fault Status Register 1, EL1, EL2 and EL3

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Hypervisor IPA Fault Address Register, EL2

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Memory Attribute Indirection Register, EL1

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Memory Attribute Indirection Register, EL2

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Memory Attribute Indirection Register, EL3

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Configuration Base Address Register, EL1

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AArch32 Virtual memory control registers

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Architectural Feature Access Control Register

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Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Data Fault Status Syndrome Register

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Hyp Auxiliary Instruction Fault Status Syndrome Register

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Memory Attribute Indirection Registers 0 and 1

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Instruction cache speculative memory accesses

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Generic Interrupt Controller CPU Interface

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About the Generic Interrupt Controller CPU Interface

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Virtual interface control register summary

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Virtual interface control register descriptions

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Virtual CPU interface register descriptions

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ROM table Debug Peripheral Identification Registers

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ROM tables Debug Component Identification Registers

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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ETM trace unit generation options and resources

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Programming and reading ETM trace unit registers

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Sequencer State Transition Control Registers 0-2

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Resource Selection Control Registers 2-16

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Single-Shot Comparator Control Register 0

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Single-Shot Comparator Status Register 0

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Address Comparator Access Type Registers 0-7

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Context ID Comparator Control Register 0

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Integration Instruction ATB Data Register

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Integration Instruction ATB Out Register

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Interaction with Debug and Performance Monitoring Unit

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Interaction with the Performance Monitoring Unit

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Effect of Debug double lock on trace register access

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Advanced SIMD and Floating-point Support

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About the Advanced SIMD and Floating-point support

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Accessing the feature identification registers

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Floating-point Exception Control Register 32, EL2

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Floating-point Status and Control Register

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Media and Floating-point Feature Register 0

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Media and Floating-point Feature Register 1

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Media and Floating-point Feature Register 2

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Coherency data channel handshake signals

# metadata.contentDescription
This document gives reference documentation for the Cortex-A73 processor. It contains programming details for registers and describes the memory system, caches, debug trace, and interrupts.