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Arm CoreLink CCI-500 Cache Coherent Interconnect Technical Reference Manual r1p0

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Arm CoreLink CCI-500 Cache Coherent Interconnect Technical Reference Manual

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Debug and performance monitoring interface

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Performance Monitor Control Register (PMCR)

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Read Channel QoS Value Override Register

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Write Channel QoS Value Override Register

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ACE and ACE-Lite slave interface signals

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Coherency data channel signals for ACE interfaces

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This book is for the Arm CoreLink CCI-500 Cache Coherent Interconnect. The CCI-500 is a programmable high bandwidth interconnect that enables hardware-coherent systems.